This page contains John's video blog related
to high-speed electronics design, FPGA digital design,
device driver development as well as general software
development. These videos are also available on
YouTube:
PCI Express Physical Layer
Published on June 8 2016, by
John Gulbrandsen
An overview of PCI Express Physical Layer Technology
- Part 1: Electrical
I will in this presentation explain:
The main problems with the legacy PCI bus that prompted the development of the
new PCI Express architecture.
An overview of the physical layer (hardware aspects) of the PCI Express bus and
how it differs from PCI.
Future presentations will cover higher protocol layers and the associated
software features.
Physical Layer Overview
Slot Connector
links and lanes
Differential signaling
Pre-emphasis
Data Scrambling
8b/10b Encoding
Embedded Clock
Clock Recovery
Data Striping
Bandwidth
Link Training
Signal Integrity PCIe Physical Layer - Keep Channel Impedance 50 ohm (SE) or
100 ohm (Diff.)
Keep PCB traces short
Length Matching
SERDES example
SERDES TX - Step 1/3
SERDES TX - Step 2/3
SERDES TX - Step 3/3
SERDES RX - Step 1/5
SERDES RX - Step 2/5
SERDES RX - Step 3/5
SERDES RX - Step 4/5
SERDES RX - Step 5/5
Analog Lab Instruments
Digital Lab Instruments
Books
PCI Express Protocol Decoding with Agilent Infiniium 54855A 6 GHz DSO
Published on Nov 18 2015, by
John Gulbrandsen
In this video, John explains how to use an Agilent Infiniium 54855A 6 GHz
Digital Storage Oscilloscope to create compliance testing eye diagrams.
Further, it is demo'ed how the included High-Speed Serial 8b/10b decoding
allows display of the 8b/10b symbols on a PCI Express Link. The oscilloscope
used is currently for sale on Ebay via the below link. http://www.ebay.com/itm/-/151888783495
A History of Windows Device Drivers
Published on Nov 18, 2015 by
John Gulbrandsen
In order to understand the architectural differences between the various
Windows platforms and the different device driver models, a historical
walkthrough of the MS-DOS and Windows platforms is provided below. As will be
explained, Windows 95 / 98 / ME have their roots in MS-DOS 1.0 that dates back
to 1981 while Windows XP and newer platforms have their roots in Windows NT
version 3.1 that was introduced in 1992. Device drivers from MS-DOS 1.0 up till
Windows 10 WDM/WDF are covered.
High-speed FPGA and device driver consultant introduction
Published on Oct 20, 2015 by
John Gulbrandsen
In this this one-hour video John walks you through some of the projects he
has done in the past and what is on his book shelves. Specifically, lots
of information regarding FPGA Digital Design, high-speed board design, device
driver and software development is given. Further information regarding his USB
and PCI Express protocol analyzer designs are briefly explained in a lab
presentation. A brief presentation of lab equipment is given. This is the first
of many of John's videos explaining practical concepts surrounding high-speed
board design, FPGA digital design as well as software engineering. These are
all skills he is offering on a consulting-basis. For detailed information
regarding his high-speed protocol analyzer designs, please see the below
videos.
ITIC 2500A PCI Express Protocol Analyzer Demo
Published on Dec 25, 2014 by
John Gulbrandsen
This video demonstrates the capabilities of John's ITIC 2500A x4 lane PCI
Express Protocol Analyzer design, which he designed and implemented all
hardware and software for between 2010 and 2014. The 2500A PCI Express Protocol
Analyzer is now available for sale at http://www.internationaltestinstruments.com at a price less than
half than competing units.
1. Overview of the ITIC 2500A PCI Express Protocol Analyzer.
2. Unboxing and overview of hardware and software features.
3. Installation of the x4 active probe between PC motherboard and plug-in card
4. Demonstration of how to setup the capture settings and trigger settings.
5. Demo of data capture and how to show and hide protocol items.
6. Demo of how to load a previously saved capture. The trace data is
pre-indexed by the 2500A PCIe Protocol Analyzer hardware after capture so
loading data from file is extremely fast. The Dynamic Data Display technology
in the 2500A Application only loads enough data needed to show the visible
protocol items on screen.
7. Explanation of how packets are displayed within higher level transactions
and how the 2500A software neatly organizes request and response TLPs and
associated DLLPs under a common higher-level transaction node.
8. Explanation of how the protocol view is created via pre-indexed protocol
item locations by the 2500A PCI Express Protocol analyzer hardware.
9. Demo of how the virtual protocol view allows instantaneous scrolling through
the full 2 gigabytes worth of trace data without any delays.
10. Demo of the Details View shows how Packet Details or Transaction Details
are decoded and displayed.
11. Demonstration of how selecting rows in the details view will highlight the
corresponding rows in the Lane View. This makes it very easy to correlate where
the decoded information originates from.
12. The Payload view now allows data to be copied to clipboard via new context
menu. The Protocol and Lane Views also allow copy to clipboard.
13. Description of how to export Protocol View and Lane View data to XML.
Markers define the start and end of the export range. Colors can now also be
set in the markers.
14. XML Export writes out all available information available in the 2500A
software so no loss of information occurs in the export process. This allows
3rd party programs to be written that post-processes the captured trace data.
15. Demo of the new, powerful Print and Print Preview functionality.
16. Explanation of how to show and hide protocol items of certain types on
certain link direction. Protocol View filtering is extremely fast due to the
design where all protocol item locations are pre-index by the 2500A hardware.
17. Protocol Item show/hide via the Node Finder view is demonstrated.
18. Demo of select and copy to clipboard is demo'ed.
19. Demonstration of how the Search Payload Data dialog now runs the search in
the background. This allows the user to continue working while long data
searches are running in the background on a separate thread.
20. Demo of the time reference, absolute and relative timestamp features.
21. Demo of the Lane View and display of a x4 lane SKP ordered set sent in
parallel on all four device to host lanes.
22. Discussion of the Protocol View and Lane View context menues and how the
commands affect the view the menu was opened in.
23. Demo of the functionality in the Capture Configuration dialog. Trigger
position, capture buffer size, link width, lane polarity and lane mapping can
be configured.
24. Description of the Trigger Configuration dialog and its eight-level Trigger
Level functionality. Up to 2048 bytes can be defined for each of the eight
sequence detectors, for a total of 16 Kilobyte byte long sequences.
25. Description of the trigger in/out external trigger port.
ITIC 2500A PCI Express Protocol Analyzer HW & SW Description
Published on Aug 22, 2014 by
John Gulbrandsen
In this video, John explains the technical hardware and software details of his
ITIC 2500A x4 lane PCI Express Protocol Analyzer design, now available for
purchase at http://www.InternationalTestInstruments.com.
This is a very complex product and the product development took approximately 4
years.
1. Overview of the 2500A PCI Express Protocol Analyzer PCB. Comparison with
earlier 1480A USB Protocol Analyzer. Description of DDR2 SODIMM.
2. Description of external PCIe x4 cable and how the external 2.5 Gbps probe is
connected to the 2500A PCI Express Protocol Analyzer.
3. Description of signal splitters on the PCIe Probe. 100 MHz PCIe refclk is
also copied and sent to the 2500A PCI Express Protocol Analyzer.
4. Description of the SODIMM DDR2 design and the associated 1.8V/3A Switched
Mode Power Supply.
5. Description of the Altera Arria II GX FPGA and the associated 0.9V/3A FPGA
core voltage switched mode power supply.
6. The PCB is constructed in 10 layers and is made with high-speed PCB
materials.
7. Description of the rear trigger port, which allows connection to external
lab instruments. The trigger port can trigger in or out, depending on settings
in the 2500A PC software.
8. Demo of the 2500A PC Software features. Most features will be ported over to
the new 1480B USB Protocol Analyzer design.
9. Demo of how to load a previously saved capture. The trace data is
pre-indexed by the 2500A PCIe Protocol Analyzer hardware after capture so
loading data from file is extremely fast. The Dynamic Data Display technology
in the 2500A Application only loads enough data needed to show the visible
protocol items on screen.
10. Explanation of how packets are displayed within higher level transactions
and how the 2500A software neatly organizes request and response TLPs and
associated DLLPs under a common higher-level transaction node.
11. Explanation of how the protocol view is created via pre-indexed protocol
item locations by the 2500A PCI Express Protocol analyzer hardware.
12. Demo of how the virtual protocol view allows instantaneous scrolling
through the full 2 gigabytes worth of trace data without any delays.
13. Demo of the Details View shows how Packet Details or Transaction Details
are decoded and displayed.
14. Demonstration of how selecting rows in the details view will highlight the
corresponding rows in the Lane View. This makes it very easy to pin-point where
the decoded information originates from. This feature will be ported to the
1480B Advanced USB Protocol Analyzer design.
15. The Payload view now allows data to be copied to clipboard via new context
menu. The Protocol and Lane Views also allow copy to clipboard.
16. Description of how to export Protocol View and Lane View data to XML.
Markers define the start and end of the export range. Colors can now also be
set in the markers.
17. XML Export writes out all available information available in the 2500A
software so no loss of information occurs in the export process. This allows
3rd party programs to be written that post-processes the captured trace data.
18. Demo of the new Print and Print Preview functionality that will be ported
over to the new 1480B USB Protocol Analyzer software.
19. Explanation of how to show and hide protocol items of certain types on
certain link direction. Protocol View filtering is extremely fast due to the
design where all protocol item locations are pre-index by the 2500A hardware.
20. Protocol Item show/hide via the Node Finder view will be ported to the
1480B USB Protocol Analyzer.
21. Demo of select and copy to clipboard is demo'ed.
22. Demonstration of how the Search Payload Data dialog now runs the search in
the background. This allows the user to continue working while long data
searches are running in the background on a separate thread. This will be
ported to the 1480B.
23. Demo of the time reference, absolute and relative timestamp features.
24. Demo of the Lane View and display of a x4 lane SKP ordered set sent in
parallel on all four device to host lanes.
25. Discussion of the Protocol View and Lane View context menues and how the
commands affect the view the menu was opened in.
26. Demo of the functionality in the Capture Configuration dialog. Trigger
position, capture buffer size, link width, lane polarity and lane mapping can
be configured.
27. Description of the Trigger Configuration dialog and its eight-level Trigger
Level functionality. Up to 2048 bytes can be defined for each of the eight
sequence detectors, for a total of 16 Kilobyte byte long sequences.
28. Description of the trigger in/out external trigger port.
29. Consulting Services are offered via Summit Soft Consulting (http://www.SummitSoftConsulting.com).
30. Summary of features that will be incorporated in the new 1480B USB Protocol
Analyzer.
31. Discussion of time invested into the 2500A PCI Express and 1480A USB
Protocol Analyzers. 9 years and 9000 pages of very detailed research notes.
ITIC 1480A USB 2.0 LS/FS/HS Protocol Analyzer Demo
Published on Aug 22, 2014 by
John Gulbrandsen
This video describes how to use the ITIC 1480A LS/FS/HS USB Protocol Analyzer
to capture high-speed USB data. The ITIC USB 2.0 Protocol Analyzer was designed
and implemented by John between 2005 and 2009. All hardware and software design
was done by John in-house and he is now offering this USB, electronics and
software expertise on a consulting-basis.
1. Overview of the 1480A front and rear panel connectors and LEDs.
2. Example capture of data exchanged between a HS Sandisk flash key and a host
computer. This demonstrates the host LED, Link Power and Link Activity LEDs.
3. Decoding Device and Host Chirp trace data.
4. Explanation of Device Requests (Set Address and others).
5. Decoding device and configuration descriptors (vendor and product IDs etc).
6. Explanation of Interface and Endpoint Descriptors decoding.
7. Decoding of IN and OUT transactions and packets.
8. Demo of how to use the Filter Dialog to hide NAKed IN Transactions and SOF
packets.
9. Explanation of how to use the Details View to decode Packet , bus events and
transaction details.
10. Shows how to use the PayLoad View to display hex and ASCI payload data of
packets and transactions.
11. Explains how to use markers and time references.
12. Demo of the Node Finder View and how to use it to find packets and bus
events in the overall trace.
13. Comparison of capabilities between software and hardware based protocol
analyzers.
14. Description of OTG SRP, VBus and HNP events.
15. Use of payload view to watch raw payload data of data and transactions.
16. Functionality of the Message View. Shows lowest-level D+ and D- data line
states as well as packets and data content.
17. Description of the Discovered Devices View. It shows all discovered devices
via use of the device descriptors obtained from the devices in the trace.
18. Demo of the Print and Print Preview functionality.
19. Overview of the 2500A PCI Express Protocol Analyzer software, which has
many advanced features that will be integrated into a 1480B version of the USB
Protocol analyzer.
20. Demo of the Search Payload Data dialog. How to find the "Cruzer Blade"
string in the overall protocol trace capture.
21. More complete overview of the Filter Protocol Items Dialog box.
22. Explanation of how to use the Filter Dialog to hide traffic to/from
specific devices or endpoints.
23. Demo of relative and absolute timestamps and how to change the time
reference in the trace.
24. Description of the 1480A Printed Circuit Board. PHY, FPGA, SDRAM and FX2LP
microcontroller.
25. Decription of planned 1480B USB Protocol Analyzer hardware changes (256 MB
trace RAM and external trigger port).
A History of PC Buses - From ISA to PCI Express
Published on Jul 13, 2014 by
John Gulbrandsen
In this presentation, John explains the major expansion buses used by the PC
platform up until PCI Express between the years of 1981 to 2004:
1) Introduction
2-4) ISA (Industry Standard Architecture)
5-6) MCA (Micro Channel Architecture)
7-9) EISA (Extended Industry Standard Architecture
10-12) VLB (VESA Local Bus)
13-17) PCI (Peripheral Component Interconnect)
18-20) PCI-X (Peripheral Component Interconnect - Extended)
21-24) PCI Express
25) Summary
