Peripheral Device Engineering...

Modern peripheral device design and implementation requires a wide range of expertise within the fields of general circuit design, high-speed PCB design, signal-and power-integrity engineering, FPGA-based digital design, microcontroller hardware design and programming, gigabit SERDES link design, memory interface design, serial channel jitter issues, microprocessor and SOC, analog design and much more.

Due to our formal training and experience in the science and art of electronics and digital design, we have the expertise required to work with the above technologies efficiently and correctly. This, in combination with device driver and application level design expertise, allows us to design overall well-working products.

If you are looking for consultants that understand the whole picture all the way from the hardware, through the device-drivers up to the application level, we are here to help!

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Past embedded hardware projects

• Hardware design and prototype development of a USB 3.0 Protocol Analyzer (ITIC USB5000A). 10-layer PCB design in Altium Designer, with blind vias and split power planes. Switched/Linear Power Distribution Network Design. SI and PI analysis in Hyperlynx. The design used an Altera Cyclone V FPGA, a 4 GB Micron DDR2 SODIMM, a 48 MHz Cypress FX2LP CPU and external TI TUSB1310A USB 3.0 PHYs. A traditional FPGA data path / controller design implemented a 32-bit byte ordering and descrambling architecture. Altera's DDR2 Controller was used. Also designed PC GUI using C# / Windows Forms. Overall, the same software architecture is used as in the below PCI Express Protocol Analyzer design. Technology: Digital FPGA Design, DDR2 Controller, USB 3.0. Environment: Quartus II, Altium Designer, Modelsim, Hyperlynx, Oscilloscope, Logic Analyzer, Spectrum Analyzer, Protocol analyzer, Visual Studio 2005 etc.

• Xilinx Virtex-5 VLX330T FPGA ADC/DAC board design. Technology/Tools: DxDesigner 9.7.4, Orcad 16.2, Cadence 16.2, Altium 13.x/14.x, VHDL, Xilinx Vivado 2013.2 and ISE 14.7.

• Software and Hardware development for Nuclear Particle Detector. Hardware (VHDL, Spartan-6 and circuit design); Software (C, C++) using QNX/Photon on an Intel platform Customer needed an expert to help them architect and design a system for the US Navy in a very short time. Interfaced with physicists to code algorithms to accurately measure radiation. Environment/Technology: Xilinx FPGA, C/C++.

• Hardware and software research and development of a 2.5 Gbps x4 lane PCI Express Protocol Analyzer (ITIC 2500A) described here. 10-layer board design in Altium Designer utilizing blind vias and split power planes. Switched and Linear Power Supply design, Signal Integrity and Power Integrity analysis using Hyperlynx, Arria II GX Digital FPGA Design using Altera Quartus II. An external active probe makes copies of the upstream and downstream SERDES data which is sent to an Arria II GX FPGA. The FPGA byte orders, descrambles and deskews the data before storing it in an external DDR2 SODIMM. The PC software then programs binary sequence detectors in the hardware which then automatically detects the location of the PCI Protocol Items in SODIMM. The PC software then uploads this meta-data and builds an in-memory tree of the hierarchical protocol item data as it appears on the bus. Data is uploaded on-demand via Virtual Tree control. Technology: Digital FPGA Design, DDR2 Controller, PCI Express 1.1. Environment: Quartus II, Altium Designer, Modelsim, Oscilloscope, Logic Analyzer, Spectrum Analyzer etc.

• Software and Hardware development for NMR Spectrometer. Hardware (VHDL and circuit design); Software (C++) development support using Texas Instruments MSP430 Microcontroller. Developed Xilinx Spartan-6 with embedded MicroBlaze processor for RF generation, NMR sequencing and digital down converting (DDC).

• Advanced R&D on high performance computer interface technologies, including PCIe, PCI, IEEE 1394, USB 2.0 / 3.0. Scatter/Gather DMA in hardware, firmware, and kernel driver space to achieve maximum system performance. Directed development of nVidia CUDA based plugin for post processing of image data, mimicking / extending capabilities found in FGPA based camera systems and for legacy (non-FPGA) camera systems.

• Hardware and software research and development of a LS/FS/HS USB 2.0 Protocol Analyzer (ITIC 1480A) described here. Logic design in Altera Quartus II 7.1. The hardware utilizes a Cyclone II FPGA which receives USB link data via an NXP ISP1505 ULPI-compliant USB PHY. The FPGA encodes the data before it is buffered in an SDR SDRAM. The data is then sent to the Host PC via a Cypress FX2LP USB Controller for further analysis. PCB Capture/Layout using Altium Designer. Signal Integrity, EMC/EMI, Prototype assembly, board bring-up, manufacturing etc. Technology: Digital FPGA Design, SDRAM Controller, USB. Environment: Quartus II, Altium Designer, Modelsim, Oscilloscope, Logic Analyzer, Spectrum Analyzer etc.

• Image Processing in Xilinx Virtex-6 FPGA. Utilized PCIe 2.0 End-Point Core. Streaming DMA interfaces. ASYNC SRAM,DDR-II DRAM, and FLASH memory interfaces. Technology/tools: VHDL, Xilinx ML605 development kit.

• FPGA digital design of a 64-port serial port adapter card for PCI Express. The plug-in card used an Altera Cyclone IV GX FPGA which utilized a hard PCI Express IP core to communicate over a x1 lane, 2.5 Gbps PCI Express link. Implemented a traditional data-path / controller architecture, 64-channel simultaneous DMA engine, custom UART designs from scratch, custom I2C controllers for I/O expansion were developed from scratch, ADC interface state machine implementation from scratch. Environment: Quartus II, Modelsim, Oscilloscope, Logic Analyzer, PCI Express Protocol Analyzer etc.

• ASIC design of PCI Express Gen 2.0 hardware offload for SSD READ and WRITE operations. Proposal of a hardware design and supporting protocol which was named "Fast IO Transport" (FIT) to support high performance PCI Express Gen 2.0 with hardware offload for READ and WRITE operations. This technology was implemented in STEC's ASIC which taped out in Q4 2010, and will be in customer eval in Q2 2011. Analyzed and fixed various software issues to allow enable STEC's second generation SAS SSD through the IBM qualification cycle.

• VME64x system controller using Altera-Aria-II GX FPGA. DDR2 shared memory controller; a 4-lane PCIe 1.1 EndPoint Controller; an SPI Bus Master; and a general I/O controller. 512Mb NOR Flash devices; 64Mb NOR Secure Flash; Altera MAX-II CPLD; 2GBytes of DDR-II memory. VME64x backplane, VHDCI interface. Technology/tools: VHDL, Altera Quartus II.

• Software and Hardware development for Software Defined Radio (SDR). Designed FPGA for SDR with VxWorks RTOS. Designed and debugged software (C, C++) for MPC860 processor in Tornado development environment. Designed radio control boards with voice codec circuitry (CVSD), ADCs, DDS, and Xilinx Spartan XC2S50 (legacy) FPGA and CoolRunner CPLD. Schematic capture using Altium Designer. Designed replacement of legacy Xilinx FPGAs with Spartan-6 family. Updated Windows software application with new user interface and controls in Microsoft Visual Studio using MFC (C++) with new controls. Created new virtual radio application using C# .NET and Java. Participated in full product release processes.

• Xilinx Virtex-5 FPGA Digital Design for RF-to Optical (5.0Gbps) board, which utilized a Fibre Channel optical interface. Technology/tools: DSP, VHDL, XiLinx development tools.

• Hyperlynx Signal and power integrity analysis on VME64x, PCI Express and DDR2 interfaces. Schematics capture, board design and SI/PI analysis. Technology/tools: Hyperlynx SI/PI, Mentor Graphics DesignerDX.

• Design and implementation of a PIC-compatible RISC CPU IP Core described here. Designed in an datapath-controller architecture. Implemented in Verilog. Environment: Altera Quartus II 6.0, Mentor Graphics Modelsim 6.0c.

• Circuit and Board design of advanced PCBs. DC-to-DC (buck & boost) switched power supply design. Schematics Capture. Mentor HyperLynx SI analysis. HSPICE, PSPICE, and LT-SPICE Power Supply Analysis. Technology/tools: Cadence Concept 16.1/16.2, Hyperlynx SI/PI, HSPICE/PSPICE.

• Analog Devices ADSP-21020 SHARC DSP, Xilinx Spartan family FPGA hardware and firmware. Design / development / integration / delivery of D/A converter board used in US Navy passive SONAR programs. Designed circuitry to extract user selected audio channel data from an ATM/SONET based towed array passive SONAR system. DMA engine, multiple D/A converters, and headphone amplifier. PCB layout constraints, parts placement. C and assembly code in SHARC DSP. VHDL code for Xilinx DMA and D/A engine. Technology: C, SHARC assembly, VHDL, Analog Devices SHARC ADSP-21020 floating point DSP, Xilinx Spartan FPGA, fiber optic ATM/SONET. Environment: OrCAD schematic capture, Analog Devices Visual DSP IDE, Xilinx ISE FPGA designer, ModelSim VHDL simulation tools, Synplicity VHDL synthesis tools, MATLAB, logic analyzer, Tektronics high speed storage oscilloscope.

• Altera Cyclone II FPGA and Max-II CPLD Design. Voice and data digitization. IP/UDP Ethernet message interface. Altera-TriMAC, Multi-port Scatter/Gather Engine; Sync-SRAM External Memory Controller; Parallel NOR Flash Memory Controller; Master/Slave HDLC Protocol Engine; Avalon-ST Interface Bus. Technology/tools: VHDL, Altera Quartus II.

• Advanced NMR Spectrometer hardware, firmware and software design. Developed an NMR spectrometer/controller from requirements, creating architecture and physical design for a startup medical device company. Used the Xilinx Virtex-4 FX family (20, 40 and 60) FPGA with embedded Power PC 405 and Ethernet MAC to anchor the design. The board integrates an LCD interface with touch screen, High-speed ADC (65MSPS) with digital frequency synthesis and digital down converter in FPGA fabric, Low-Speed Delta-Sigma ADC, 10/100 Ethernet, USB, RS232, DDR SDRAM, flash PROM, RTC, microSD, GPIO SE and LVDS and MICTOR debug components.
  
  The board also manages over ten different power systems from a single 5V input. Architected and wrote data acquisition and signal processing logic for FPGA in VHDL and with IP cores using the Xilinx ISE. Developed the processor support system in the Xilinx XPS with VHDL and Verilog. Designed and wrote real-time server firmware for Power PC using the Xilinx SDK to manage I/O, acquire and store data, and respond to client requests to retrieve data. (5000+ lines of C) Designed and wrote a client application with Visual Studio in C++ using the MFC/ATL libraries for a user interface to the data server. (8500 lines C++) Created schematic design and BOM, transferred design to PWB layout designer, and debugged finished PWAs.

• FPGA/DSP/uC-based Pixel Array Detector hardware, firmware and software design and implementation. Developed a complete system, creating requirements, architecture and physical design for an advanced scientific instrument. Refined the design through multiple generations to prototype. The first generation was built with a Xilinx Spartan-3 FPGA mated to Analog Devices SHARC ADSP-21065L DSP-based board with Rabbit processor Ethernet controller. Firmware was written in C and Rabbit and SHARC assembly languages to control the instrument. The second generation used a multi-FPGA solution and proprietary inter-board communication bus. The SHARC processor was replaced with the embedded Power PC 405 processor integrated into the Virtex-4 family.
  
  Each Power PC controller communicates with 4 XC4VSX35 FPGA based controllers that de-serialize high speed output from a 512x128 Pixel Array Detector ASIC. ADCs are integrated onto the controllers to acquire residual signal from the ASICs. The completed system results in a 512x512 array detector. All logic was written in VHDL with the use of IP cores where available. Designed and wrote real-time firmware for the Power PC in C and assembly language. Created an Ethernet stack to support 10/100/1000 Ethernet with UDP. Designed and wrote support software on a host Windows computer in C++ language with Visual Studio using MFC/ATL libraries for test and debug purposes. (12000+ lines of C++) Created a remote interface to Linux systems for spooling data to central storage using Windows sockets. Designed a thermoelectric cooler (TEC) controller to regulate temperature of the ASIC detector chips.

• DSP and FPGA based Analog/Digital Controller Board. Schematic capture; FPGA/CPLD VHDL coding & simulation; and pre/post PCB layout & route signal integrity analysis. Floating-point DSP (TMS320C6727); fixed-point DSP micro-controller TMS320F2812 predecessor to the TMS430; Virtex-4 (XC4VFX20) for RocketIO, Gigi-bit Ethernet & Hot Link communication links; Xilinx CPLDs; 200Khz sampling rate ADCs (AD974), DACs (AD5764) and Resolver/Syncho-to-Digital converters (RD19230).

• Data Acquisition hardware and software for electromagnetic field surveys. Designed next generation data acquisition board anchored by XC3S4000 FPGA with embedded soft MicroBlaze processor. Created schematic and BOM and transferred design to PWB layout designer. Managed the PWB layout. The design integrates USB, Ethernet 10/100, RS232, SDHC memory card slots, SRAM, GPS receiver with disciplined oscillator and 9 channels of data acquisition (100KHz) running synchronous to universal time. Created new drivers for existing firmware design to interface GPS device using Xilinx EDK. Tested and debugged system. Modified existing Windows based ATL application to utilize new GPS controller.

• Buck switched power supply design utilizing DC-to-DC buck switches / LDO's for digital power conversion and only LDO's for analog power conversion. Power Sequencing circuitry. Over/Under voltage detection circuitry.

• USB 3.0 webcam consisting of a 1280x800@60fps MIPI image sensor and stereo microphone inputs as well as an Altera Cyclone III FPGA which was used for audio/video processing functions including Bayer filter demosaicing and a pulse density modulation (PDM) to pulse code modulation (PCM) conversion module.

• Actel FPGA and Lattice / Xilinx CPLD design of 2 Gbps encrypted data communication board. Power supply design involved Pi / Low pass filtering networks; 5V-to-3.3V DC-to-DC conversion (Buck switcher); Under/Over monitoring with hysteresis; Battery with trickle charge; and tamper circuitry.

• Tactical Cross Domain Ethernet Switch FPGA based on a Xilinx Virtex-5 FXT device for use in a military application. Design contains both Microblaze and PPC processor subsystems and provides physical isolation between the various packet processing nodes as well as various security and anti-tamper features.

• FPGA development of a Bi-static Control Card containing an Altera Stratix-II GX FPGA which is used to synchronize multiple instrumentation radars via a multi-gigabit fiber optic link. Also responsible for a repackaging of current 220mm VME PCBs

• Magnetic Resonance Imaging medical device design and implementation. Engineered all aspects of the product, including electrical, mechanical, signal processing and technical documentation. Acquired UL listing and CE mark, and directed transition to manufacturing. Architected and designed product electrical and industrial system design. Developed and maintained company's signal processing controllers: standalone Virtex-4/PPC based and PC hosted Motorola DSP56002. Converted system from PC hosted to standalone Ethernet and wireless 802.11A/B/G.
  
  Wrote the system firmware in DSP56002 assembly and C. Designed, debugged and tested multiple generations of 8 MHz, 5KW peak, RF transmitter. Designed, debugged and tested multiple generations of 200V, 50A pulsed linear gradient amplifiers. Designed, debugged and tested 8 MHz ultra low noise amplifier (<1 nV/√Hz). Evaluated numerous components in analog designs including but not limited to power FETs, FET drivers, low noise GAsFETs, OpAmps, transformers, high voltage components and other passive and active components.
  
  Characterized behavior and optimized performance of each design. Created and optimized PWB layout using PCAD and produced Gerber files. Managed engineering group of hardware and software engineers. Acted as primary manufacturing engineer responsible for transferring all engineering developments to production in compliance with FDA and ISO guidance.

• High speed digital/analog electronic radar transceiver boards (LINK-16 waveform processing). This hardware implemented waveform processing via IBM PowerPC µPs, 167Mhz SDRAMs, and several TI TMS320C64x (6416) DSPs.

• FPGA development in instrumentation radar project which included arbitrary waveform generation, precision timing pulse generation, data acquisition control, and real-time DSP including variable integration modes, grouping capabilities, pulse phase correction, bi-phase demodulation, data normalization, and support for multiple tracking modes. Responsible for ongoing support and enhancements for all FPGA designs in the radar.

• Single board computer for a space ship. The design includes: a PowerPC, 2 FPGAs, and 2 ASICs. The SBC is designed to RadHard specification, for use in outer space. The operating system is VxWorks.

• PCI Target Xilinx Spartan-II FPGA for Virtual Instrumentation product including PCI bridge, pulse generation module, memory-mapped host I/O, and discrete control of on-board resources. Also developed RF Control, System Status Monitor, DUT Control Module, and Pulse Generation FPGAs for next generation PXI-based virtual test instrument.

• Hardware design of the PCI Dump Switch Card described here: http://www.summitsoftconsulting.com/DumpSwitchCard.htm. Analog and Digital circuit design. State machine implementation using both discrete gates as well as a 16V8 PLD. Used WinCUPL to implement the PLD state machine code. Schematic and layout work was done in Protel. Prototype assembly. Technology: Analog/Digital design, PCI-bus. Environment: Protel, Oscilloscopes, WinCUPL.

• FPGA-based flight simulation projector which provides the ability to dynamically reposition and retime digital video of various resolutions and sync rates using a reprogrammable PLL controller and internal line buffering.

• Designed digital / analog electronic CPU boards. Network Interface board comprised of dual QLogic Fibre Channel ports and a 16-pair LVDS backplane link. Board packetizes digital video, voice data and analog data at rates up to 70MBytes. Technology/tools: Viewlogic, Orcad 16.0, Cadence Concept.

• FPGA-based 32-channel real-time processing card that contains a Xilinx Virtex-II Pro FPGA which accepts a complex input at 50 MSPS and uses a polyphase decimating filter bank and 16k block FFT to provide target spectral information to downstream processing for a mobile tracking radar system.

• FPGA-based Integrated a narrowband digital receiver card with a 14-bit, 200MSPS input, containing a DDC, 4 independently tunable NCOMs, and multiple programmable decimation filter stages in a Xilinx Virtex-II Pro for a phased-array radar receiver project.

• FPGA-based contrast enhancement for NTSC or PAL composite video via multiple digital filter stages and a histogram equalizer.

• Altera 1K30 & 20K60E FPGA telecom boards. HDSL4-to-T1 and G.SHDSL-to-E1 trunk interface. VHDL code responsible for system timing, I/O control, and address decoding for an E1/V.35 to dual pair G.SHDSL card. Developed a NEBS, FCC, and UL compliant T1 to HDSL4 line card. Design cycle steps involving schematic, layout, debug, and first pass integration. Technology/tools: Viewlogic, Altera-VHDL, Allegro 14.2.

• FPGA-based frequency spectrum analyzer that accepted chirp-modulated input from an ADC and demodulated the input to baseband utilizing a set of nine decimating resolution bandwidth filters, and also provided both linear and logarithmic signal power computation, video detection, and frequency analysis.

• Print controller FPGA design using a PCI-based SBC in order to incorporate a digital phase-locked loop, improved motor control, and improved image registration for a four-head color digital photo printer unit with pulse-width modulated (PWM) outputs.

• DDR SDRAM controller IP module operating at 133/266 MHz using a V600E for customer. Repackaged design and retargeted for all Spartan-II, Virtex-E, and Virtex-II devices and packages to be used as a MemecCore IP Core product and meet Xilinx requirements to be listed as an AllianceCore.

• FPGA-based 16-channel UART IP Core for MemecCore. Developed functional specification, verification plan, and HDL. The device contains one microprocessor interface and all necessary registers, FIFOs, and logic to emulate sixteen industry-standard UARTs.

• Voice/data processing ATM line card (OC3 & DS3 line rates). Schematic, PCB layout, debug, and integration. Major design components were the MPC8260, IPCAM3, Sync SRAM, PIC16F877, PLX9054 and XCV1000 FPGA. Dual redundant Compact-PCI backplane for data/voice communications. LXT970 10/100Base-TX Ethernet transceiver coupled with the MPC8260s MAC sub-module for external diagnostic communications. Eight layer PCB board stack-up. Technology/tools: OrCad, Xilinx-Verilog.

• Serial Access Memory (SAM) controller section on PCI image card of next generation print controller. Created 64-bit DMA controller FPGA that communicates with an AMD 29k embedded processor in order to share image data between a 2GB SDRAM array, a 2MB SRAM buffer, and two banks of synchronous FIFOs.

• Hardware and software design of an USB-to-telephone converter. Used for interfacing telephones to standard PCs via USB port. Hardware design, electronics schematics, PCB layout and prototype building. Used DirectSound and DirectInput for low-latency streaming sound and control. Used Microsoft TAPI for call-control in test applications. Technology: USB, Electronics CAD applications (Protel), COM. Environment: Visual C++, oscilloscopes and other normal HW development tools.

• SCSI, OC-3 Print Controller Adapter Board design, including product specification, schematic entry, PCB layout, and programmable logic for two custom Altera CPLDs in VHDL. Board provides OC-3 fiber optic interface from Varis print controller to the SCSI interface of OEM print engine.

• ATM based xDSL Integrated Access Device. Implemented detailed digital/analog circuits design utilizing the MPC860P, TMS320VC5409, 10KE30 FPGA, GlobeSpan DSL chipset, and PMC-Sierra T1/E1 Comet. Card processed voice via AAL2 and data via AAL5. Ten layer PCB board stack-up. Technology/tools: Viewlogic, Altera-VHDL.

• ADSL Modem card. Created digital/analog circuits (including EPLD) which utilized Alcatels' (MTK20140) chipset and the Virata-Helium network processor. Six layer PCB board. Technology/tools: Viewlogic, Altera-VHDL.

• PCI-Bus based T1/E1 trunk interface boards. Intel 430HX (Embedded Pentium-II) chipset. Twelve layer board. Technology/tools: ViewDraw, Altera-AHDL, Vantis-Boolean, HyperLinks.

• RF based automotive security hardware module (INKEY system). Design utilized RF Amplitude Modulation and Manchester Encoding technology to control engine ignition. Technology/tools: Mentor Graphics, Altera-AHDL, 68K ASM, H-Spice.

• Digital/analog hardware and assembly programming for a multi-product diagnostic acquisition system (MDAS) for automotive Body Computer Modules. The MDAS design utilized an HC16 micro-controller and Altera 7128 EPLD. Technology/tools: Mentor Graphics, Altera-AHDL, 68K ASM, H-Spice.

• TMS320C30 DSP based board. Implemented 2-D image processing. Image processing techniques performed were Segmentation, Histogramming, Moment Extraction, and Moment Summation. Designed and compiled C language scripts for hardware checkout and debug. Technology/tools: ViewDraw, ViewSim, H-Spice, Altera-AHDL, Actel, ANSI-C, Mentor Graphics.

• Asynchronous parallel to serial & serial to parallel interface board. This PCB card transmitted and received asynchronous analog (via A/D conversion) and digital data. Technology/tools: ViewDraw, ViewSim, H-Spice, Altera-AHDL, Actel, ANSI-C, Mentor Graphics.

• Digital/Analog Circuit design for Close Circuit Television Systems, Power Inverters.

• Design and implementation of a waveform acquisition module. Performed layout on a densely populated five-layer printed circuit board.

• 8080, Z80, 8086, 80186/2911 Hardware and firmware design. Designed and implemented software and hardware to test communications equipment, including concentrators and switches. Processors include 8080, Z80, 8086, 80186, and a proprietary bit-sliced (2911) processor. Developed test system and software.
  Past embedded software projects

• USB and File System Drivers for QNX RTOS. QNX mass storage driver, USB host controller driver, USB class driver, QNX file system driver, troubleshot performance problems and flash corruption problems. USB protocol analysis with protocol analyzer. Technology: QNX RTOS, USB 2.0, Flash Memory, Environment: USB Protocol Analyzer.

• USB Video Class (UVC) firmware for USB 3.0 image sensors. Implemented USB 3.0 video class (UVC) customized Firmware for on Cypress USB FX3 chip. UVC video imaging firmware design and debugging. Technology: C and C++, ARM assembly, Environment: Cypress FX3 SDK, Eclipse, USB protocol analyzer.

• Linux OpenSSL AES 128 TCP/IP Client/Server Application Development. Using OpenSSL (HTTPS) principles developed a Linux, C, C++, TCP/IP Socket based Client-Server Application to transfer Encrypted Data. AES 128 bit Encryption Cipher was used for Encryption/ Decryption. This Client Server app was developed to transfer Patient Records.

• GNU TCP/IP C/C++ kernel firmware for VoIP Satellite phone and modem. ARM Cortex based Freescale Kinetis MCU. Designed firmware algorithms for PBX call forwarding, call routing, packet data network connections. Multitasking using sockets, inter-process communication and shared memory. Kernel mode scheduler for power management, voice and data call management. Program Battery Operated Mobile Devices where battery life management is key. GPS devices and protocol, SIP server and SIP client, SMTP, POP3, DHCP, PPP, IP routing. Technology: TCP/IP, VoIP, ARM Cortex, RTOS. Environment: Visual Studio, embedded GNU C/C++.

• Ported existing RTOS with ThreadX RTOS in existing code base. Reverse Engineering of SSD storage device firmware, especially in the transport (SATA) area. Technologies/tools: ARM v7-R: Cortex-R4: Thumb2, Multi (Green Hills/GHS) IDE, ThreadX, SSD (Solid State Drives): NAND flash

• Embedded C Linux application development on Motorola PPC750 processor based board. This Application controlled various sensors to monitor, process, report weather data. Developed a Socket based File Transfer Utility to load the Application Software into Linux, report collected data, statistics to a Server.

• UEFI BIOS Platform Software. Developed Dell Provided Features (DPFs) in UEFI BIOS environment, working with ODMs, OBVs, and Platform Vendors, as well as other disciplines with Dell. In-depth consulting regarding PC Architecture, DMTF Industry Standards, and the latest developments in Platform Architecture and System Manageability. Developed UEFI BIOS specific tools for monitoring SMBUS traffic as well as other aspects of BIOS and Platform behavior.

• Linux-based C/C++ Multi-threaded Image Processing (License Plate Recognition) TCP Server to perform Optical Character Recognition on an Intel i7 based mother board controlling an IP Camera. It involved cropping of the digital images based on the pixels positions as obtained via FrameBuffers from the Camera. Implemented Load Balancing to improve overall performance and throughput. Also implemented software based control & monitoring of image quality due to changes in lighting conditions. Also developed code on an Atmel Microcontroller to control a sensor device.

• Embedded Linux set top box built on a Broadcom chipset. Developed system bootstrap and directfb components.

• Software and Hardware development for Nuclear Particle Detector. Hardware (VHDL, Spartan-6 and circuit design); Software (C, C++) using QNX/Photon on an Intel platform Customer needed an expert to help them architect and design a system for the US Navy in a very short time. Interfaced with physicists to code algorithms to accurately measure radiation. Environment/Technology: Xilinx FPGA, C/C++.

• Research and Development for new imaging unit within Thorlabs. Developed camera related software and firmware. Responsible for system architecture, API design and implementation, host to camera command and control, interface design, and documentation. Host software lead for USB 3.0 development. Perform integration of Thorlabs catalog items into our host software package, including third party cameras and other camera-related peripherals. Responsible for specification, oversight, and senior level development of system/unit testing, installation package, and all facets of the OOBE for our customers. Responsible for OEM support and aide in business development. Technical liaison for Third Party Application Support. Involved in cross-BU software development group responsible for setting corporate coding standards. Cypress FX3, Microchip PIC32, Microsoft Visual Studio 2008/2010, C, C++, C#, Altera FPGAs, and Installshield are relevant technologies involved.

• Application, driver and firmware for a bio-medical device doing DNA extraction. Driver for CAN (C_CAN) bus and all of the layers of application code. Development of five system modes for a system consisting of 30 microprocessors (9 unique), 5 Tecan pumps, 36 stepper motors, and other peripheral devices. Development / modification of PC support programs in Visual Basic and Visual C++, including hex2bin, bin2hex, program download, parameter download, and start times generation. Development of bootstrap loader including boot (zero) record. System and sample statistic generation and storage into database. Research, porting, and writing of efficient square root routines. Firmware control of 8051 internals including timers, UARTs, Flash, and ADC. Technologies/tools: 8051: Silicon Labs C8051F06x, C8051F12x: Keil C and Assembler,, code banking, OMF51, IDE; ARM v7-M: Luminary Micro Stellaris LM3S892 Cortex-M3: Thumb2, Eclipse IDE, Code Sourcery, Stellaris Peripheral Device Library; Tecan Pumps (XLP6000); Barcode Readers (NLV1001, NFT 2100/2200).

• Linux Multi-Threaded SSL Offload mechanism on a Xilinx FPGA based Ethernet card. Using OpenSSL (HTTPS) package on Linux. Developed Linux based Ethernet Driver as a Linux Kernel Module to implement the SSL Offload Engine to work with the TCP/IP stack. Based on Cryptographic Ciphers Modified SSL stack to have Encryption/ Decryption offloaded on the FPGA HW. Implemented a secured File-Download in this platform.

• Hardware and software research and development of a 2.5 Gbps x4 lane PCI Express Protocol Analyzer (ITIC 2500A) described here. 10-layer board design in Altium Designer utilizing blind vias and split power planes. Switched and Linear Power Supply design, Signal Integrity and Power Integrity analysis using Hyperlynx, Arria II GX Digital FPGA Design using Altera Quartus II. An external active probe makes copies of the upstream and downstream SERDES data which is sent to an Arria II GX FPGA. The FPGA byte orders, descrambles and deskews the data before storing it in an external DDR2 SODIMM. The PC software then programs binary sequence detectors in the hardware which then automatically detects the location of the PCI Protocol Items in SODIMM. The PC software then uploads this meta-data and builds an in-memory tree of the hierarchical protocol item data as it appears on the bus. Data is uploaded on-demand via Virtual Tree control. Technology: Digital FPGA Design, DDR2 Controller, PCI Express 1.1. Environment: Quartus II, Altium Designer, Modelsim, Oscilloscope, Logic Analyzer, Spectrum Analyzer etc.

• Embedded Linux set top box based on custom ASIC. Diagnosed and corrected problems with early hardware versions and schematics. Wrote kernel drivers and modules to initialize system resources, cooperate with co-processors, and realize new board features. Resolved third-party firmware issues in cooperation with vendors. Implemented shell scripts to load co-processors and initialize the system features.

• Performance enhancement of 8051-based GPIB driver in C. Continuing/sustaining engineering: Bug fixes, new features, code cleanup, dead code/variable removal, code reorganization, major code rewrite; code speedup by factor of 15; size reduction by a factor of 10. Porting of features from one product to others; combining source code from three products to single source. Improvements to GPIB driver. Conversion of assembly code to 'C'. Assist in hardware debugging. Technologies/tools: 8051: Avocet Assembler, Keil C, Nohau Emulator; GPIB (IEEE 488.1, 488.2 Bus), National Instruments utilities (NI Spy, GPIB Analyzer), TNT4882

• Linux C/C++ Multi-threaded Networking application development via configuring the Cavium Octeon (MIPS Core) processor on a Network Access Card to implement Network Access Security via Network Intrusion prevention. This involved the design of Host SW controlled Network Access Rules, Unified Access Control and respective Actions to filter Traffic. Via Multi-threaded programming, implemented on the Multi Core Cavium Octeon Chip Rule based Packet Classifiers, Rule based Packet Actions, and Packet Flow Tables to monitor Network Traffic.

• Linux-based Network-Attached Storage (NAS) component of client's high-volume, high-availability video surveillance products.

• Development of firmware, kernel mode drivers, API libraries, and applications level software for high end scientific digital camera systems. Block level hardware design for PCIe, USB, and 1394 interfaces. FPGA based imaging microcontroller to support advanced imaging and system integration. Developed instruction set. Was a key player in development of technology for precise timing of FPGAs for maximum CCD performance - forming the core of the client's most advanced camera systems.

• Embedded Nucleus RTOS drivers and firmware. MPC860 internals including chip selection and memory mapping. Drivers for MPC860 with Nucleus Plus RTOS; Fast Ethernet Controller (FEC) using MII, SCC Ethernet (OQUICC), UART, I2C (with microcode patch). Drivers for various flash parts: AMD, Atmel, Intel; Interface to PCI using PLX9054. Nucleus Plus internals including Nucleus File with Intoto's Flash Media Manager (FMM). Research into Target Monitors using internet (web) resources; modification of monitors by Hitachi and Tasking. Development of boot code for Fiber to the Home product; Hardware/software integration and debugging. File loaders for ELF and 'S' formats; interfacing with program download. Porting of Multiport's IP/UDP stack TFTP. Technologies/tools: MPC860/855T, Nucleus Plus RTOS, Nucleus File, Intoto FMM, Diab Assembler, C, Broadcom BCM5606, PLX9054, LXT971A, Wiggler/OCD/BDM. LAN/VLAN/MAC (802.1D, 802.1Q)

• Software and Hardware development for NMR Spectrometer. Hardware (VHDL and circuit design); Software (C++) development support using Texas Instruments MSP430 Microcontroller. Developed Xilinx Spartan-6 with embedded MicroBlaze processor for RF generation, NMR sequencing and digital down converting (DDC).

• C/VxWorks Device Driver BSP development of a High Speed Proprietary Networking Protocol using Xilinks FPGA chips on a Proprietary NIC. This NIC used a FPGA based HW assisted Pt-2-Pt Fibre Channel Communications Link. Implemented a Proprietary Buffer Structure Mechanism for the HW chip to process frames. Designed and implemented SW Redundancy which performs Automatic Link Switchover upon the detection of a Faulty Link. Implemented FPGA Image upgrade via this VxWorks BSP. Besides, on another NIC implemented Socket Layer Interception Mechanisms, Linux Kernel Threads.

• Wind River Linux and VxWorks Board Support Package (BSP) development for company's Fiber To The Home (FTTH) line terminal boards, primarily those that used Gigabit Passive Optical Network (GPON). The line terminal boards were based on Broadcom's FASTPATH switching hardware/software solution. Built company's Linux development capability by creating custom distros to deploy development and infrastructure Linux machines. Gathered requirements and implemented open-source solutions for source control and other configuration management functions.

• Embedded VxWorks RTOS firmware development. Wrote SNMP like interface protocol between management unit and line units for both T1 (HDSL/2) and E1 (ETSI). Ported VxWorks BSP (Board Support Package) to MIPS NEC VR4121. Fixed bugs in existing ETSI products. Technologies/tools: 8051 Family: Assembler, Keil C, Signum WEMU51 Emulator, Zilog Z180: Assembler, IAR80 C, Softaid UEM Emulator, MIPS: NEC VR4121: VxWorks (Tornado II), Assembler, GNU C & Make.

• Advanced R&D on high performance computer interface technologies, including PCIe, PCI, IEEE 1394, USB 2.0 / 3.0. Scatter/Gather DMA in hardware, firmware, and kernel driver space to achieve maximum system performance. Directed development of nVidia CUDA based plugin for post processing of image data, mimicking / extending capabilities found in FGPA based camera systems and for legacy (non-FPGA) camera systems.

• Hardware and software research and development of a LS/FS/HS USB 2.0 Protocol Analyzer (ITIC 1480A) described here. Logic design in Altera Quartus II 7.1. The hardware utilizes a Cyclone II FPGA which receives USB link data via an NXP ISP1505 ULPI-compliant USB PHY. The FPGA encodes the data before it is buffered in an SDR SDRAM. The data is then sent to the Host PC via a Cypress FX2LP USB Controller for further analysis. PCB Capture/Layout using Altium Designer. Signal Integrity, EMC/EMI, Prototype assembly, board bring-up, manufacturing etc. Technology: Digital FPGA Design, SDRAM Controller, USB. Environment: Quartus II, Altium Designer, Modelsim, Oscilloscope, Logic Analyzer, Spectrum Analyzer etc.

• Policy-controlled software MAC using OTS WiFi components. For both 802.11 and 802.16d chipsets, designed MAC modifications to add the frequency agility and ad-hoc functionality that XG requires.

• WinCE 5.0 Modem interface. Proprietary device on MX31 ARM platform running Windows CE 5.0. Develop NDIS intermediate miniport driver as primary component of device. Implement streams and message queue interface to said driver for communication with central driving application. Modify boot loader code for FPGA and DSP modules. Develop build system for Windows CE 5.0 environment. Configure RNDIS functionality for host connection to device. Implement encryption support using Windows Cryptography API. Develop application that automatically-updates software employing device notification. Create "safe" WinCE image and modify BSP boot loader for fail-safe device boot. Create USB 2.0 Host class driver on Windows CE 5.0 platform for client's proprietary device.

• Implemented SCSI III Medium Changer, 200 Disc DVD Changer, 1394, Am188 RTOS/Firmware, Windows Driver Development. Development environment used Paradigm C++ Professional Linker / Locator, RTKernel-C on embedded x86. Ported RTKernel-C RTOS from PC/DOS environment to Embedded / Paradigm environment. Project was showcased as a main stage keynote demo for WinHEC 1997.

• Embedded C/assembler development for in-flight entertainment product. Porting of LAPD protocol package from Retix/Trillium to OS-9 as "server" process. Code/debug Hardware/Software interfaces. Developed Diagnostic Software package for DMUX & ISDN cards. Drivers for Siemens Conferencing chip and for two Flash Memory chips. Exerciser for ISO stack under OS-2 (layer 5). Realtime Voltmeter with Thermistor curve fitting. Technologies/tools: Motorola: 68331: OS-9: Microware C, Introl C, Assembler, Nohau Emulator, PCXWARE, Novell.

• Embedded Linux Networking Application development (IP, MPLS) via configuring the Agere Payload Plus (APP) Network Processor. Using PowerPC as a Host Processor running Linux as a RTOS. Assembly Language Microcode Programming to implement IP/MPLS based Pattern Matching & Packet Classification, Packet Forwarding, Bandwidth Policing, Packet Shaping, Packet Scheduling, and HW based very fast Data Path Switching of Packets. Used C/App550 FPL in this project.

• Satellite GSM/GTRS/UMTS terminal running VxWorks on an ARM/XScale processor. Gathered product requirements and led a team of three engineers to realize the security features unique to the terminal. Also implemented multiply-redundant satellite return/uplink using multicast IP on a Windows 2003 NOC Server.

• Joint Strike Fighter Panoramic Cockpit Display Firmware development. Two Freescale Power PC 7448 processors control the LCDs. One uses Greenhills Integrity, and the other, the embedded Linux LynxOS. Both are D0178-B certified operating systems. OpenGL is the graphics engine interface. The firmware will also be certified to D0178-B, MISRA-C++, and SEAL standards. The LDRA tool set is used to maintain standards. The workstation uses Red Hat Enterprise Linux.

• MA-361 Six Channel Remote Controlled Audio Distribution Amplifier. Developed COP8Flash Firmware controlling amplifier modules, volume / tone and graphic EQ modules via digital I/O, over SPI and I2C.

• Phone Control GUI tool for GSM & WCDMA chipsets. Interfacing via DLLs to control Audio, RF, battery, Power Management Unit, and Display. Developed Instant Messaging Client application, Media Browser application, Timer applications, Stopwatch application, mobile basic calculator and Media player application for mobile phones using propriatary framework and platform tools. Environment / tools: VC++ & Borland C++, phone simulator & network simulator.

• Nucleus RTOS embedded firmware development. Modified NUCLEUS File System (similar to MS-DOS). Developed/modified video record/play algorithms for Video Data Recorder (VDR). Development of Reclaim algorithm to re-use disk space. Modifications of On Screen User Menus for VDR. Generalize debugging of existing code for VDR including Hardware/Software interfaces. Technologies/tools: MIPS RISC 3051: NUCLEUS Real-Time OS: MetaWare High C, Assembler, Embedded Performance (EPI) tools, C-Cube JPEG CODEC (CL560), DSP, GANDIVA RAID.

• Quantenna BSP and 802.11 wireless driver for proprietary hardware. MAC adjustments for a long-range link. Porting Atheros ath9k PCI-E NIC driver into ARC BSP. Developing GPIO driver to control Tx power, LEDs, etc.

• VxWorks (Tornado), Linux, C, C++ Multi-threaded Embedded Firmware that Controls and Manages a PowerPC based Head End Router connected to Cable Modems. This Router used Radio Frequency Technology based Modulation Techniques for the network communication between Cable Modem and Head End Router. Defined, Implemented the SNMP Agent based Management Architecture to manage the Head End Router, Radio Frequency Interfaces, and configuration parameters as needed. Designed & Implemented Web Pages (GUI) to have a Southbound SNMP interface to the Switch. Implemented SNMP API Functions so that HTML based Apache CGI Application can Send/Receive SNMP Messages to manage the Chassis. Following an Object Oriented Design approach defined Company specific MIBs via ASN.1 & implemented them under VxWorks. Used VxWorks (Tornado), Linux, C, C++ in this Project.

• VxWorks and Linux cross-platform environment in C. Extended the VxWorks simulator to reflect anticipated hardware at a HAL/BSP interface. Implemented expanded network capabilities and high-speed timers for simulator. Ported existing Linux VOIP monitoring and call generation software as well as third-party MGCP and RTP toolkits to new framework.

• Embedded PowerPC firmware and device drivers. Wrote firmware driver and download program for CSM/3 chip.Implemented UART driver for one of ports of the MPC860. Assisted in design and porting of code which was split between two CPU's to run on a single CPU. Hardware/software integration: BSP for MPC860, trouble shoot board, design power-up and diagnostics. Modify/review hardware design to make software more efficient. Team leader (3): defined/scheduled tasks and monitored progress. Fixed bugs in existing code base for other products (DMC). Technologies/tools: Motorola MPC860 (PowerPC) [similar to 68302], Assembler, C, Rockwell (Conexant) CSM/2. CSM/3 (Digital Central Site Modem), ARM Controller.

• TCP/IP QoS Priorith Queing design and implementation. This involved the design of a Priority based Multi-tasking Preemptive Scheduling mechanism.

• Embedded Firmware Development for Hitachi SH-2, Z180. Signature Series 3.0 DVD Player Firmware- flash update, serial interface protocol (RS232/RS485) and firmware driver development for Signature and Citation Series DVD Player, Six Axis Surround Processor, and Preamp / Tuner. Windows based Flash Update System for high end audio equipment.

• Bootloader for the PowerPC-based AP-600/TMP-11 AP family. Co-designed security features, startup sequence, and manufacturing process.

• Micrium uCOS-II RTOS firmware for ARM7 board. ARM7 NXP LPC2468 microprocessor, embedded C drivers for SPI, I2C, UART, D/A, PWM, and LCD controller peripherals. Embedded IP file system and GUI libraries from Micrium interfaced to microSDHC media card and QVGA LCD. Embedded C firmware on Micrium uCOS-II RTOS provided user interface and real time water quality sensor data. Technology: C, ARM7 NXP LPC2468 microprocessor, Segger Jlink, microSDHC media card, Micrium GUI library, Micrium FS file system library, Micrium uCOS-II RTOS, SQLite embedded database. Environment: IAR EWARM IDE.

• x86 Platform BIOS Development. Responsible for building different variants of BIOS images in a cyber-security capacity. Employ Arium JTAG emulator for flashing images and debugging. Work with customer to develop proprietary binary parser for BIOS images. All activities performed ahead of schedule and delivered under budget.

• SNMP Agent Design and implementation that performs Automatic Reload of system Configuration due to System ReBoot.

• SAS driver for the LSI SAS 1064 Controller on the Nucleus RTOS. Implemented application-level API that included all standard SCSI commands. Supports dual-port SAS drives. Implemented SATA over SAS on the controller via STP (SATA Tunneling Protocol). Technology: C/C++, Nucleus RTOS. Environment: Mentor Graphics Edge debugger.

• Blackhawk and Chinook helicopter Firmware. Development of an AAS, (Alert Audio System), for the DCU, (Data Concentrator Unit), of the Blackhawk and Chinook helicopters, using the Analog Devices BF535 Blackfin DSP. Also WIN32 programs to interface to the target, for test and backdoor control. Code development to interface the Texas Instruments TLV320AIC23B Audio Codec to the BF535.

• Custom PowerPC-based single board computer bring-up. Implemented a boot loader based on PPCBOOT (now u-boot) and ported embedded Monta Vista Linux.

• Tftp/Ftp based software Image upgrade between File Server and Switch via customizing VxWorks bootcode.

• Software and Hardware development for Software Defined Radio (SDR). Designed FPGA for SDR with VxWorks RTOS. Designed and debugged software (C, C++) for MPC860 processor in Tornado development environment. Designed radio control boards with voice codec circuitry (CVSD), ADCs, DDS, and Xilinx Spartan XC2S50 (legacy) FPGA and CoolRunner CPLD. Schematic capture using Altium Designer. Designed replacement of legacy Xilinx FPGAs with Spartan-6 family. Updated Windows software application with new user interface and controls in Microsoft Visual Studio using MFC (C++) with new controls. Created new virtual radio application using C# .NET and Java. Participated in full product release processes.

• VxWorks SNMP Network Management design and implementation, for a Chassis based DSLAM Switch using VxWorks Operating System. It involved Multi-threaded Design, Development and Implementation of a SNMP Agent SW, Configuration Data Storage on Flash Memories, Programming of Various Hardware Registers, Proprietary MIBs Development & Processing of SNMP Requests etc.

• Telephony T1/E1/HDSL System and Application software. Controlling interface between HDSL and V.35, RS-449, DSX-1, G.703, X.21, and combination of ports. Improvement of diagnostic/selftest/burn-in test software package. Improvement of user interfaces (dumb terminal & front panel). Development of HDLC interface to remotely control/monitor multiple boards in single rack; development of RS232 packet oriented interface to SNMP & NMA network controllers for multiple racks of multiple boards. Technologies/tools: 8051 Family (80C32, 80C535, 80C552, 87C751): Archimedes C, Franklin C, Assembler, Nohau Emulator, Chip View.

• Joint Strike Fighter Avionics Interface Adapter (AIA) Firmware and software. The AIA provides a gateway for 1394 communications to other interfaces, including 1553, 232, and 422. Firmware development to interface the Analog Devices ADSP-2183 DSP, to the TSB12LV32I/TSB81BA3 1394 Firewire Link-Layer controller and three-port cable transceiver/arbiter, for the network interface on the JSF,(Joint Strike Fighter). Also WIN32 test set, using the FireBoard 800 by Unibrain, which will transmit 128 byte packets every 12 ms., and continuously receive 128 byte packets simultaneously. Yokogawa and FireSpy 1394 data analyzers were used for testing.

• Symbian OS 6.1 Application Development. Developed Mobile-walky application over Bluetooth using Bluetooth framework of Symbian OS 6.1 and tested it in NOKIA 7650. Environment / tools: C & C++, Microsoft Visual Studio 6.0, Symbian Series 60 SDK.

• Linux SNMP/MIB Event-Management to Manage and Process Alarms (SNMP Traps). Designed State Event Models to manage Boards and Report Alarms (SNMP Traps) from various Devices. Architected an innovative fast mechanism to implement Performance Monitoring of huge number (1000+) of ports (DSL Interfaces) via the MIB Defined "Interval Tables" and Performance Metrics Objects.

• Embedded display system firmware for military aircraft. Built VxWorks code to drive graphics display, video streaming, and control proprietary hardware. Mocked up Linux-based COTS prototype to develop on prior to hardware delivery.

• ARM Cortex M3 STmicro STM32F103 Embedded C++ firmware for handheld water meter and velocity/depth sensor interface. Embedded C++ firmware drivers, SPI, I2C, UART, D/A, PWM, NOR flash, keypad controller, and LCD controller peripherals. Embedded IP file system and GUI libraries from Micro Digital and Micrium, interfaces NOR flash drive and QVGA LCD. Embedded C++ application code was designed around the Micrium uCOS-II RTOS with Quantum Leaps QP Framework state machines provided user interface and real time sensor data. Technology: C++, ARM Cortex M3 STmicro STM32F103 microprocessor, Segger Jlink, NOR flash, Micrium GUI library, Micro Digital FS file system library, Quantum Leaps QP Framework, QVGA LCD. Environment: Keil uVision5 IDE

• High altitude missile Software design and development. Power PC single board computers using VxWorks and Tornado control the missile after launch. The Portable Launch Station uses a Graphical User Interface developed with Visual Studio 2005 and Visual C++. Star Team is used for software change and configuration management. DOORS is utilized for software requirements. The Bouml UML tool was used to accomplish the OOA, (Object Oriented Analysis), and the OOD, (Object Oriented Design). Microsoft PowerPoint was used to create the presentation for the CDR, (Critical Design Review).

• VxWorks Flash memory device Drivers that facilitates very fast efficient Save/Load of Config-Files under VxWorks Environment. It also included the Design of Automatic Reload of the Chassis-Configuration in the event of a System ReBoot. Used VxWorks (Tornado), Linux, C, C++.

• Intel Atom and Atmel AT91SAM Embedded firmware development for Polymerase Chain Reaction (qPCR). Brought firmware development in house from third party developer and documented embedded system. Developing (C++) and debugging in Linux on Intel Atom (IA32) architecture using Eclipse IDE. Developing (C/C++) and debugging in IAR workbench on Atmel AT91SAM (ARM7). Programming and debugging in Visual .NET C#/C++ application. Programming and debugging for Ethernet sockets (server and client side). Automated testing of optical and thermal elements of the PCR machine.

• Management Agent SW design and implementation. The software controls and manages the Network Elements (NE) of an ATM-Frame Relay (HSS1100) Switch. This included design & development of a Common Library Software for Multi-threaded Reentrant Handling of Protocol Data. Wrote a number of Design Docs for the Design of Common Library Software Architecture. This Library SW was used to Control, and Configure the NEs in the Switch.

• Car Infotainment system with telematics, for an American auto manufacturer. Communication channels include: CAN Bus, LIN Bus, and USB. Multimedia features include: DVD, various audio specifications, navigation, real-time route planning using emergency information, and satellite audio and video. Design tools include: Telelogic DOORS, Rational Clearcase, Microsoft SharePoint, and Telelogic Synergy.

• Linux Device Driver and Firmware. Design and develop software applications to manage SNMP-enabled telecommunication network devices. Develop network timing synchronization firmware for telecom network devices to comply with CableLabs Certification in Embedded Linux. Implement SNMP agents and management station software, SNMP protocol layer implementation in C/C++. SNMP v1, v2c, v3 agent development, traps, NET-SNMP, MIB, MIB browser. Displays remote telecom sites, network elements and managed optical devices in a hierarchical tree view.
  
  Provides a single unified display of SNMP alarms for up to 100 networked optical devices. Design and develop a Web-based, SNMP proxy agent that enables users to remotely configure and control optical equipment. Automatically discovers optical network equipment, detects associated SNMP traps and alarms, and send alarms to higher-level network management station (such as HP OpenView) via SNMP. Web UI and CLI interface implementation, Javascript and HTML coding. C/C++, Monta Vista embedded Linux target, Fedora host dev platform 2.6 kernel, GNU make, toolchains. CableLabs Certification process, testing and development to meet CableLabs requirements.
  
  Hot Swappable PCI based network device software infrastructure design, hot swap software engine to identify insertion/removal of boards, handle the hot swap event with system services and drivers. Linux multi-threaded networking firmware programming and debugging. TCP/IP Network socket programming and IPC communication mechanism implementation. IPv4 and IPv6 configuration, NIS and DNS host name address resolution. Linux kernel programming, LKM, serial port Linux driver, U-Boot bootloader development.
  
  Linux performance monitor firmware development (MTIE, jitter, frame error rate, etc). System availability monitoring, alarm and event management. CLI interface via serial console, SNMP interface, and Web interface design. Technology/Environment: Embedded Linux, Fedora , C/C++. SNMP v1, v2c, v3, NET-SNMP, MIB, MIB browser, Hot Swappable PCI, TCP/IP Network sockets, IPv4 and IPv6, NIS and DNS, LKM, serial port Linux driver, U-Boot bootloader.

• Windows CE communications driver to facilitate data between CE application and two mcp2515 CAN transceivers.

• Developed pinsetter and touch screen interfaces, remote software update for Instant Replay Processor, game development, NVRAM and software update for Scoring System in Watcom, Borland, Phar Lap TNT, multi-threading message state machine based x86 development environment. Also developed PC Based serial interface protocol analyzer.

• Defined MIBs and Implemented Network Management Primitives to Provision, Configure NE. This involved Processing of Q.2931/ Q.931B Signaling Messages, Configuration of ATM PVCs via PVC End Points and CrossConnects between them. Besides implemented Bandwidth Management and Network Provisioning of Service Level Agreements for Different Classes of Service. Also provided support for SW Redundancy for various Switched Connections in the event of a Link Failure.

• Red Hat Enterprise Linux Software design and development for the ICS, (Integrated Computer Systems), component of the BCTM, (Brigade Combat Team Modernization), replacement for FCS, (Future Combat Systems). The UML OOA/OOD design tool utilized, is the Rational Rose Enterprise Edition. Rational Clearcase is the version control software, and Rational Clearquest is used for software bug tracking. Rational DOORS provides the document and software requirements management tool. Two operating systems are used: Red Hat Enterprise Linux and the LynxOS POSIX and ARINC 653compliant time and space partitioned version of Embedded Linux.

• C SNMP Agent to run under LINUX to Monitor a Switch. Implemented a Buffer Management Library SW for the Layer2 Data Path Processing of Packet Switched Data. Provided mentoring to junior Team Members. Used C in this Project. In this Project Object Oriented Design Methodology was followed and various Data Structures were implemented to Provide Object to Object Communications so that NE performs SNMP Operations such as GET, GET_NEXT, SET, TRAPS (Alarms).

• Embedded microcontroller programming in C/assembly. Designed electronic data collection systems for vehicles used in transportation research projects. Programmed embedded Motorola 68HC11 processors in C and assembly language. Interfaced third-party systems to proprietary data collection systems using RS-485 and RS-232.

• Military sensor fusion system Firmware development. The Atmel AT91RM9200, (ARM 9), provides the basis for the WNC, (Wireless Network Controller). Slaves to the WNC include a Blackfin 561 which performs the image processing, and a mesh radio, which is used to communicate with several wireless smart sensors. Iar provides the embedded IDE, and MicroC/OS-II is the real time operating system. Visual C++ is used to develop the HMI program, which provides command and control of the WNC, and displays the images with MTI, (Moving Target Indicator). An industrial climate control network, which uses a TDMA differential interface, was developed. A proprietary voting system of PID is used to minimize KWH rates, by reducing peak usage. TI MSP430 microcontrollers are used.

• NETWORKING (Q.931 Signaling) Software implementation for a TR-303 Digital Loop Carrier Digital Loop Carrier (DLC) Switch. This involved Implementation of OSI based Network Protocol Q.931 in order to process the various Networking (Signaling) Messages in the Switch. For this Designed and Implemented State-Event based FINITE STATE MACHINE as per the Q.931 Protocol. 

• PCI Express firmware, hardware, drivers, UEFI and legacy BIOS, and support applications for the STEC Enterprise class PCIe SSD. This technology was done in an FPGA based design and was designed into the STEC's 4th generation SSD ASIC design. Set up a development lab, acquire equipment, schedule and plan the debug and integration of the system. Java enterprise configuration application and Windows and Linux enterprise drivers.

• BSD Unix based embedded system firmware and driver architecture design and implementation, system level debugging and verification, testing and QA planning. C and C++ programming, debugging, testing on BSD UNIX. TCP/IP network programming. Design and develop 802.11WIFI wireless kernel device driver. Peripheral PCI device drivers for touch-screen monitor, international keyboards, USB device driver, Thermal Printers with USB and serial interfaces, etc. Design internationalization (i18n) and localization solutions for GUI applications. Install-base sustaining, bug fixing and system maintenance, complete product life cycle development. QA test planning, testcase design, white-box and black-box tests, automation tests, test tool design. Technology/Environment: FreeBsd, C and C++, TCP/IP, 802.11WIFI, PCI, USB, Thermal Printers, QA test.

• PSOS Inter-Task Communication with LAPD Protocol for the LAPD link, based on the principles of Automatic Protection Switching mechanisms. Developed Fault Tolerant SW to achieve SW Switching of the Standby Line upon Failure Detection of the Active Line. Used PSOS as Operating System and C/C++.

• Embedded and Windows 7/8 USB software and firmware design for the client's mobile TV, audio and video solutions. Architectural design and development of USB software on new IPTV chip product from scratch. IPTV device firmware based on ARM7TDMI processor and toolchain. Analog and digital video, DVB-T and DVB-H protocol, MPEG, YUV encoding and decoding. Chipidea USB IP stack modification and integration. Help hardware team make architecture decisions, e.g. Hardware buffer size requirement analysis. Video and Audio USB class driver and firmware development, High Speed USB 2.0 specification. Bulk, Interrupt, and Isochronous USB transfer, descriptor and endpoint priming, queue heads, etc. Debugging and troubleshooting with Ellisys and CATC USB analyzer, A/V decode, frame analysis. Windows WDM and WDF host USB audio and video driver design, and integration with device firmware, using DirectX, DirectShow, DirectSound, AVStream. RGB and YUV format, encoding/decoding. Technology/Environment: USB 2.0, ARM7TDMI, DVB-T and DVB-H, MPEG, YUV, Chipidea USB IP, Video and Audio USB class, WDM and WDF, DirectX, DirectShow, DirectSound, AVStream RGB and YUV.

• Vehicle controller RTOS Firmware development, using the Motorola 68360 processor, with the MQX real-time operating system. The controller is capable of utilizing various communication protocols, including LON, which utilizes LONWORKS, and operates with the Echelon chip.

• Q.931, X.25, LAPD+ Protocols network GATEWAY Interface development. Involved Translation of Packet Switched X.25 Calls into Q.931 based Signaling Messages during Call Establishment, Data Transfer, Call Clearing. It required Cross-Mapping of Q.931 IEs into X.25 based Facilities.

• Texas Instruments TMS320-based Signal Processing Programming. Signal conditioning from industrial sensors. Technology: C/Assembly. Environment: TI Code Composer.

• DSP algorithms for mobile air defense radar system. Digital electronics Systems Engineering, radar HW/SW control loops, sub-array DSP algorithms, and other critical radar performance functions.

• Frame Relay Network C Software for a client/server Operations Monitor. Developed Software to manage X.25 Interface Operations in the Data Network. Developed Test Plans for the X.25 Protocol on IDACOM Protocol Analyzer.

• Embedded System communications device Firmware development, using the Atmel At91 Arm processor, with the IAR Embedded Workbench and FreeRtos. The CML Microcircuits MX604 modem with SRI radio, allows wireless, real-time command and control with a master and up to 4 slaves. Other communication interfaces include RS232, RS422, USB, and Bluetooth.

• USB Protocol Analyzer Debugging between custom device and W2003. Technology: Use of ITIC 1480A USB Protocol Analyzer.

• VOIP Pocket PC software development. Low latency implementation of a Voice over IP (VoIP) software phone for the Toshiba Pocket PC. The solution incorporates the RTP stack and is complied with the Robust Audio Tool (RAT) specification.

• Military communications test equipment drivers and applications. VXI-based, (similar to VME), embedded Linux board with the MPC8245, (Power PC 603e core), Integrated Processor. The workstation is Debian Linux Intel and the embedded Linux is TimeSys 2.6. Four, (4), communication devices are on the Power PC board, and device drivers were written for each. Control scheme consists of custom WIN32 applications software talking over either TCP/IP with sockets, or VXI Visa commands, which control the embedded Linux communications.

• OSI Network Layer ISDN Q.931 Protocol development. Central Office based Call Processing Software with regard to OSI Network Layer based NET-WORKING involving Q.931 Protocol for ISDN Connectivity.

• Embedded Linux Software development for the Future Combat Systems, program. Specifically for VMS, which is part of MCS. Using Embedded Linux, SlickEdit, Rational Rose Real Time, ClearCase, and ClearQuest.

• A voice compressor/decompressor for Digital Cellular Subscriber Unit complying with the VCELP IS 54 EIS standard (contracting for the DSP Group) implemented on a multi processor platform based on the TI( 320C51 Digital Signal Processor. In addition, fast algorithms of convolutional and block error correction were developed and implemented along with the voice tasks

• FreeBSD-based SAN storage software with an emphasis on networking protocols and multi-threaded kernel space software, device drivers, volume managers, and SAN management for FCP and iSCSI. FreeBSD and UNIX kernel and application programming in C and C++. Networking protocol implementation in TCP, UDP, sockets, DNS, NIS, NFS, etc. Debugging of issues found during test execution drive those issues to closure with QA team. Kernel level debugging with GDB and KGDB, core dump analysis, root cause analysis. Technology/Environment: FreeBSD/UNIX , TCP/IP, FCP and iSCSI, TCP, UDP, sockets, DNS, NIS, NFS, GDB and KGDB.

• RADAR processing system embedded design and development, to MIL-STD 498, using PowerPC on the VME-bus with the PSOS operating system and the SUN SOLARIS workstation.

• ATA disk drivers for the Nucleus RTOS. Supported both ATA and Vendor-specific commands. Technology: C/C++, Nucleus RTOS. Environment: Mentor Graphics Edge debugger

• Linux and Windows 802.11n WiFi drivers on Atheros AR9130 chipset, Broadcom and Marvell chipsets with Integrated MIPS, MAC, Baseband and ADC/DAC. Design and Develop Bluetooth high performance devices. Develop Linux 2.6 based kernel driver, BSP, MadWiFi driver, and USB based WiFi device drivers, LTIB (Linux Target Image Builder) to deploy BSPs (Board Support Packages) for various target platforms. Develop Windows 7 and Windows Vista WDF NDIS Miniport network drivers based on the latest Microsoft Windows 7 device driver architecture, device stage, device metadata packaging, etc. Develop 3G/WiMAX kernel driver for security, intrusion detection and blocking features for the company's WiFi analyzer software suites.
  
  Develop VoFi (Wireless VoIP) analyzer software to analyze and pinpoint wireless communication issues for clients. Implement application to integrate with Cisco Call Manager protocol engine into VoFi analyzer to analyze Cisco VoFi phone call statistics, QoS metrics and identify problem areas. Develop 802.11a/b/g WIFI driver on Atheros 5212 based on PowerPC IBM405GP platform running Denx ELDK embedded Linux, on MiniPCI Atheros Wifi card. Ubuntu Linux host dev platform. Read Mini PCI IBM 405 data sheet, troubleshoot PCI register configuration problems. MadWifi Soft AP access point configuration shell scripts, AP management CLI and Web interface in CGIC scripts and thttpd web server.
  
  Fix interrupt handling problem in interrupt service routines. Design and develop Linux kernel (2.4 and 2.6) software and device drivers for multi-service business gateway devices which integrate VOIP, Ethernet, DSL, and T1/E1 WAN interfaces. C and C++ in real-time embedded Linux and VxWorks U-Boot bootloader programming, UBoot customization, board bringup. Linux kernel ramdisk based image programming, TFTP protocol. Technology/Environment: 802.11n WiFi drivers, ADC/DAC, Bluetooth, Linux 2.6 Kernel, BSP, MadWiFi, Linux Target Image Builder, 3G/WiMAX, Wireless VoIP, 802.11a/b/g WIFI, Atheros 5212, PowerPC IBM405GP, embedded Linux, Ubuntu Linux 2.4/2.6, VOIP, Ethernet, DSL, and T1/E1 WAN, C and C++, VxWorks U-Boot, TFTP.

• Software development for a vision system for SMT, using the Analog Devices BF535 Blackfin DSP and the Analog Devices RTOS VDK. Communication drivers for the 1394, (Firewire), SBP-2 interface.

• Telephone Call Processing Software on GTD5 Switch. Development of Call Processing Features such as Call Waiting, Conference Calling, Call PickUp, Announcement Processing on GTD5 Switch. Developed Test plans for Q.931 & LAPD Protocols on TEKELEC Protocol Analyzer.

• Windows CE 2.1x PCI Drivers. Ported vendor's Hitachi SH-3 PCI-based reference platform from Windows CE 2.11 to 2.12. Employed PCI bus analyzer to diagnose problems in vendor's PCI bridge controller for various devices such as EIDE disk, NE2000-flavor network interface card, and video adapter.

• BSP (Board Support Package) for a custom CPU board using the Atmel AT91RM9200 ARM-based micro-controller. The BSP included device drivers for five on-board four-channel Oxford Semiconductor OX16C954 UARTs as well as drivers for various on-board peripherals. Brought up the CPU board with the use of logic analyzers and oscilloscope. Made various prototype hardware patches. Technology: ARM Assembly, C/C++, Nucleus RTOS. Environment: Mentor Graphics Edge debugger, Oscilloscopes, logic analyzers.

• Pulse-pair preprocessor module for a naval radar system using a mix of fixed and floating point DSP operations and also developed the embedded microprocessor subsystem and microcode to communicate with a downstream processing computer via a gigabit Ethernet link.

• Software development for Range Safety Systems. Missile telemetry data acquisition system command and control of the Omega System 3000. The software is built using Visual C++ 6.0. The Telelogic Rhapsody UML tool was used to accomplish the OOA, (Object Oriented Analysis), and the OOD, (Object Oriented Design).

• WinCE 4.2 RF communications driver for Psion Netbook PCMCIA card.

• Firmware development of a military motion tracking vision system. The design includes: * PowerPCs: 755, 8245, and 405, (Xilinx EDK). * 5 Xilinx FPGAs. Code development of board level BSP and drivers for the VxWorks Wind River Platform for Industrial Devices. Tornado 2.2 and Single Step is used for debugging.

• WinCE 5.0 LCD Driver for Samsung ARM9 S32410 BSP. Added KITL support for debugging and downloading thru the USB interface (RNDIS implementation).

• Firmware and tool design for Medical Devices. Develop, maintain and enhance system software for defibrillators, pacemakers and other medical devices. Develop, maintain and enhance firmware and low level real-time device drivers to monitor internal digital signals and generate required signal patterns and waveforms for the breadboard device. Touch screen display, watch dog, Multi-threading, Process/Thread management. Develop and maintain a Python based regression test suite of Python scripts for testing hardware device drivers. Extensive use of Windows Python WMI service interface library calls and GUI interface with Python Pmw megawidgets and Tkinter module. WinSock, Network Driver development, Kernel development and debugging, IPC.
  
  Logic analyzer is used extensively to verify signal waveforms and real-time timing performance requirements. C, C++, MFC, Python, Perl, RTX Real-Time Windows Extension System. Write design specification, validation and verification plan and procedure documents, and test reports to meet stringent FDA requirements. Wind River development tools. C and C++. Reverse engineering large code-base without pre-existing documentation, bug fixing and troubleshooting USB 2.0 embedded system firmware for medical devices, create design documents. Nucleus Plus based host OS, Atmel USB core, Mass Storage Class library, Bulk transfer. Inter-process communication, memory management.
  
  Write technical specifications and documentations targeted for FDA validation and verification process. Develop software tools in Python, Perl script languages for validation. Develop automated test system to initialize the medical device, perform the functional test, and capture test results in machine-readable form to enable automated analysis. Technology/Environment: Medical devices, Touch screen, RTOS, Windows WMI, Python, WinSock, NDIS, IPC, Logic analyzer, C, C++, MFC, Python, Perl, RTX Real-Time Windows Extension, Wind River RTOS, USB 2.0, Nucleus RTOS, Atmel USB Core, Mass Storage Class, FDA validation.

• TCP/IP stack for Proprietary Internet Appliance. 8-bit microcontroller, (Motorola 68HC11), using the Cirrus CS8900 Ethernet controller in 8-bit mode. Visual C++ 6.0 development for the PC side using MFC, and UDP and TCP/IP Sockets. PIC 16 firmware for an audio signal injection device. WDM device driver for Windows 2000. Communication device driver for a Linux embedded system, that translates from Ethernet to RS232, in order to facilitate data acquisition from an Ethernet Set Top Box to an RS232 68HC11 embedded system.

• Design and development of a network stack for the Nucleus embedded RTOS. Also developed several client and server applications over the network stack that allowed an embedded application to communicate with various WIN32 services provided by a PC on the other side of a USB link. Technology: USB, Networking. Environment: Visual C++, Mentor Graphics CodeLAB.

• Implementation of WinCE 6.0 BIOS, BSP, and Drivers on AMD x86 GEOD board.

• IBM Embedded Speech Systems SDK for VxWorks Design and development. QNX (Neutrino), and Windows CE. Support of APIs for voice recognition and text-to-speech. Also, tool development using Visual C++ 6.0/MFC.

• SLOTTED ALOHA protocol simulation model development for Random Access Communication Networks. MC6800 Assembly Language, Electronics Designs.

• Linux and Windows Device Driver and firmware development, create device specification based on hardware datasheet, open source device driver code for BIOS, NAND flash, USB, SD, wireless and mesh network, Graphics, Display Controller, Camera, HID (mouse, keyboard) and battery operated devices. Reverse engineering open source device driver, firmware and application code, write hardware and software specification documents based on the reverse engineering result. Create technical specification based on hardware schematic and device data sheets, register settings, hardware and software interfaces, timing related hot fixes, power management, test and debugging.
  
  Device driver development, testing and debugging. Design and develop OS switching technology on i386 PCs. C and C++, Modify Linux 2.6 kernel ACPI, power management, suspend/resume routines. Create utility program that loads multiple kernel images, suspend-to-RAM. i386 architecture C and assembly programming. Performance tuning and timing benchmarking and tests. GIT version control. Technology/Environment: Device Drivers, Firmware, BIOS, NAND flash, USB, SD, wireless, Graphics, Display Controller, Camera, HID (mouse, keyboard), Linux 2.6 kernel, ACPI, GIT version control.

• VOIP (Voice Over IP) cable system Design and development. Using the Motorola 8260 QUICC, VxWorks, and Tornado 2.0. Initial board bring up, and BSP development. The Telogy Golden Gateway with the Texas Instruments 5421 DSP is used to process the constant bit-rate PCM stream.

• MC6800 based Data Acquisition System to record Employee Attendance Data, calculate Salaries. Developed Software for Temperature Scanning & Monitoring Systems using INT8085 processor.

• Hardware and software design of an USB-to-telephone converter. Used for interfacing telephones to standard PCs via USB port. Hardware design, electronics schematics, PCB layout and prototype building. Used DirectSound and DirectInput for low-latency streaming sound and control. Used Microsoft TAPI for call-control in test applications. Technology: USB, Electronics CAD applications (Protel), COM. Environment: Visual C++, oscilloscopes and other normal HW development tools.

• OOA/OOD of SATCOM software defined radio, (SDR), using Motorola 68360 H/W, and PSOS RTOS/compiler/linker. Object Team is used for UML analysis and design. Design and development of communications I/F between the 68360 radio and the 87C51 COMSEC processor. Design and development of driver class for the 68360 SMC auxiliary port. WIN32 embedded simulation using Microsoft Enterprise version of Visual C++, and MFC,(5.0). Encryption design and development, (COMSEC). ANDVT protocol. Diagnostics software design,(BIT).

• Aeronautical video and audio entertainment systems Software Design and development. A CAN network of PIC 16/17 microcontrollers is employed to control video, audio, power supplies, relays, etc. MPLAB and CCS tools are used for the embedded firmware. Microsoft Enterprise version of Visual Basic, Visual C++, and MFC, (5.0), are used for the numerous utilities required to control, configure, and test the system. Microsoft Access database format is used to provide customized configuration of the system for each application.

• Low-level RS-232 interface coded in C needed to communicate with remote Proportional Integral Differential (PID) controllers used in silicon growth laboratories at Wright Patterson Air Force Base.

• BSD Unix based embedded system firmware and driver architecture design and implementation, system level debugging and verification, testing and QA planning. C and C++ programming, debugging, testing on BSD UNIX. TCP/IP network programming. Design and develop 802.11WIFI wireless kernel device driver. Peripheral PCI device drivers for touch-screen monitor, international keyboards, USB device driver, Thermal Printers with USB and serial interfaces, etc. Design internationalization (i18n) and localization solutions for GUI applications. Install-base sustaining, bug fixing and system maintenance, complete product life cycle development. QA test planning, testcase design, white-box and black-box tests, automation tests, test tool design. Technology/Environment: FreeBsd, C and C++, TCP/IP, 802.11WIFI, PCI, USB, Thermal Printers, QA test.

• Aeronautical instrument test set,(ADTS), software design and development. Calibrates and cycles altimeters, air speed indicators, and MACH air speed indicators. WIN32 program that creates user profile scripts for the ADTS. Software used includes: MSVC++ 1.52 and 4.0, MFC, GREENLEAF tools, and PVCS.

• Windows CE Network Driver for 10/100 Base-T AMD chip.

• SAP to PC DOCS interface software design and development, using MSVC++ 5.0 with COM.

• Design and development of an embedded Hitachi H8 Micro controller system. Design and implementation of a pre-emptive real-time kernel for it. (Round robin scheduling, pre-emptive time slicing, Semaphores, msg queues, timers and more). Design and development of a multithreaded real-time application for the device. HW Technology: Flash memories, USB controller, UARTs, Hitachi H8 CPU, PLDs, emulators and Logic Analyzers. SW Technology: Operating system implementation, real-time programming.

• Reflection emulator Ole Automation WIN32 DLL Design and development, to adapt OLE interface to an existing program that uses Windows HLLAPI for control of Attachmate and RUMBA emulators. Versions for Windows 3.1, Windows 95 and Windows NT. Using MSVC++ 4.2 and 1.52,and BC 5.0.

• Debugging of hung Windows CE 6.0 OS Image with Platform Builder 6 for TabletPC.

• Nucleus Plus RTOS and ARM Firmware Engineering. Develop user interface task that is part of a digital camcorder product. Write C and C++ firmware code dealing with camera LCD on-screen display status. Design a firmware state machine to respond to user button presses, handle external and internal events. Based on Nucleus Plus RTOS and ARM processor. Communicate with product marketing to define feature set and coordinate with hardware and system integration groups to finalize design and clear design obstacles. Technology/Environment: Nucleus Plus RTOS, ARM Firmware, C and C++.

• 8051 assembly firmware development for V.32bis central site modem. Many modes include Hayes dial, 2 wire, and 4 wire lease lines. Using dual Intel 8051 controllers and assembly language.

• Digital/analog hardware and assembly programming for a multi-product diagnostic acquisition system (MDAS) for automotive Body Computer Modules. The MDAS design utilized an HC16 micro-controller and Altera 7128 EPLD. Technology/tools: Mentor Graphics, Altera-AHDL, 68K ASM, H-Spice.

• Hardware/software development of a distributed multiprocessor system consisting of 15 CPU boards that controlled an automatic paper testing system. This system communicated with a data analysis system implemented in Delphi 2.0 under Windows NT. Measured data was stored in a MS SQL-server 6.5 or Borland Paradox. Technology: Programming in a real-time operating system and direct to the hardware in C and Assembler. Emulators and Logic analyzers.

• Embedded RTOS firmware for Set Top Box data acquisition system, including communication, LCD, and touch screen drivers, using the 68306 MCU with GNU tools and PSOS/RTXC real-time executive, and 8032 MCU with Franklin tools. Conversion of PSOS to RTXC. Windows communication S/W using Visual C++. Networking software for 486 head-end controller running QNX,(Unix).

• VxWorks USB firmware and device driver project. Develop USB peripheral device driver firmware for digital still camera and USB printers. Implement USB peripheral stack and peripheral class drivers for device enumeration, control transfer, bulk in and bulk out data transfer, isochronous and interrupt transactions on VxWorks and Nucleus Plus. PowerPC and ARM7TDMI based microcontrollers. Test and debug with JTAG, CATC protocol analyzer and sniffer tools.

• RTXC RTOS 68302 and 68HC11 networked, fire control system, using RTXC real-time executive, SDS and Archimedes compilers, and HP and HMI emulators. Design and coding of all startup routines and SCC communication drivers for 68302. Windows communication and download programs were developed, using Visual C++.

• video subsystem design utilizing JPEG, H.261, MPEG1, and MPEG2 compression standards utilizing Motorola's proprietary chipset. Technology/tools: View logic, MC-Spice, Synopsys, ANSI-C.

• 1394 Firewire device driver design and development.

• 68HC11 interactive CATV Set Top Box (STB) FW, using Archimedes compiler and Nohau emulator. The STB has many multimedia capabilities, including real time multiuser gaming and streaming media with MPEG. Windows diagnostic program that downloads code to 68HC11 flash eeprom memory, using Visual C++.

• Develop 802.11 WIFI device driver and firmware, MAC layer firmware design, Access Point firmware, implement WEP encryption and authentication algorithm.

• VMEbus-based digital controlled radar I/O and timing (RIOT) for an imaging commercial avionics Millimeter Wave Radar System. Technology/tools: ViewDraw, ViewSim, H-Spice, Altera-AHDL, Actel, ANSI-C, Mentor Graphics.

• Design, implement and test OSGI and Residential Gateway (RG) or Home Gateway multiple RTOS device drivers firmware for USB, Ethernet, IrDA, HDLC communication protocols for Linux and VxWorks. Implement firmware interface of RG hardware core. Device driver design, coding, regression test, document and demo software development in C and assembly.

• Motorola 68HC11-based embedded controller Software and hardware design. POCSAG decoder, used to provide an integrity check of base station paging data, using Introl assembler and C. Software development was done on an Apollo workstation using the Introl compiler and linker, under DSEE version control. Creation of an Apollo-based simulation program to facilitate debugging of controller software before hardware was available. Real-time emulation was provided by Pentica.

• Maintain a Windows 98 IrDA VxD to debug asynchronous I/O issues in serial virtual driver to communicate with the IrDA hardware.

• Intel 8096-based embedded controller automated telephone answering system, using C and Borland C++, connected to a network of Intel workstations using IRMX,(PLM), and then to TANDEM computers. Software debugging was aided by Softscope. Voice signal processing programs running on a PC were written to aid in the voice message recording phase.

• Radio base station controller firmware developmment, for a cellular phone system, using a Seimens 80c537 microcontroller, (8051), and PLM51-ASM51 tools with proprietary kernel. Development of cell site controller simulator, using Compaq 386, Microsoft C 5.1 and Borland C++ with VRTX real-time executive. The emulator was supplied by Nohau.

• Develop IrDA IrOBEX, IrTranP protocol stack in C. Develop UML object-oriented demo software for USB and IrDA protocol stack in Visual C++ to show digital image transfer and device inter-connectivity.

• Optical Time Domain Reflectometer (OTDR) software using multiple processors. An 80286 is configured as the main processor, with an 8088-based data acquisition system communicating with it through dual-port ram. Tools used include : Masm, Microsoft C, Faraday Bios, Rom Dos, GFX graphics tools, and the multi-tasking real-time executive AMX86.

• Embedded FIR/IIR/FFT filter design and implementation. Developed waveform digital filtering program to analyze the effect of various types of filters on heart beats. The program allowed the application of lowpass and highpass (FIR and IIR) filters as well as implement an FFT to analize waveforms in frequency domain. Developed real-time, multi-tasking software for analog data acquisition and control of CELIA System. The system is used in hospitals, for monitoring heart patients at home, directly from the hospital. The language used was Paragon Professional Pascal. The system is currently in Beta test at Holy Cross Hospital. Also developed heart beat classification software in Pascal, used in an embedded application using digital filters and correlation. This software acquired and classified heart beats in real-time. 

• Motorola 68XXX processor RTOS R&D. Designed hardware-independent graphics library for M68XXX. Designed image processing software for Data Translation board. Designed X.25 communication hardware and software for VME bus, using WD2511 chip. Designed VME Bus circuit board and drivers for the Texas Instruments TMS32020 DSP. Extensive experience with MS-DOS, and IBM compatible computers, (Masm, Tasm, GW Basic, Quick Basic, Turbo Pascal, Turbo C, Microsoft C, Quick C, Modula-2, Turbo Prolog, and Microsoft Fortran).

• Embedded USB communication protocol firmware using C and C++ on RTOS Embedded Linux, VxWorks and Nucleus Plus.

• Navigation and local information system design for vehicular use with map display and voice output, Sensor fusion scheme using GPS and dead reckoning. One version of this system used multiple processors, (68000, 68020, 80286), communicating in real-time on the VME bus through shared global memory. Large data base design is done on the VAX, (VMS), and implementation of the real-time location dependent data retrieval system, (TELEMATICS), is on the multi-processor computer, and also on a COMPAQ 386. Pascal, C, and Assembly language were employed in the design of the M68XXX processors.

• Bluetooth Link Controller and Link Manager firmware for link level security features, encryption and authentication algorithm based on Bluetooth standard. Implement UPF and TCRL tests. All firmware done in C on 8051 microprocessor. Implement a HCI driver testing tool software in C, generating pseudo random test files containing all Bluetooth HCI commands and other protocol transactions.

• Pseudo random test case generator tool in C for Java performance enhancement semiconductor IP over the Internet. Use standard XML and Java bytecode at assembly level, generate thousands of Java Class files containing random sequence of Java JVM bytecodes. Cover testcases including recursive calls, all standard Java bytecodes, and all complex random sequence. This C language testing tool is extensively used by internal hardware design and verification teams.

• Intel 80188EB and 8031 processor Software and hardware design, RF Monitor System, used to analyze radio activity on a network-based vehicle automatic location system. Software tools include Borland C++, Paradigm linker/locator, and Archimedes C. Real time emulation was provided by SLD.

• Windows CE based portable medical data acquisition device. Subprojects included: 1) Specification and development of Windows CE device drivers for data acquisition, 2) Windows sockets communication over infrared link (IrDa), 3) Application programming using WIN32API, Visual C++ and MFC for Windows CE. Environment: Windows CE, C, C++, Embedded toolkit for VC++.

• Development of BIOS for portable, 486-based pen computer with Opti or Acc system chips, including smi-based power management strategy, using Masm and Microsoft C, SOFTICE and Codeview debuggers.

• Microcomputer design and development of an embedded DC-motor controller. The motor controller was based on a Intel 80196CA CPU which controlled the position and speed of the DC-motor. Technology: A mixed environment with a real-time operating system and direct programming of the hardware in C and Assembler. (IAR and O´Tool). Emulators, debuggers and logic analyzers.

• Assembly language and C Maintenance of Crosstalk Mark 4 product. Code for this communications software was developed using assembly language, (Optasm), and C, (Microsoft). Periscope debugger was used.

• Vehicle equipment and accessories software, for automated tests of HP Basic computers controlled the testing via HP-IB bus, (now IEEE-488).

• Development of a Logic Analyzer targeted to run in MS-DOS. The application was used as the interface for a logic analyzer, which sampled data from a microprocessor system. The communication with the sampling hardware took place via a parallel ISA interface board. Functions for disassembling sampled data (Motorola 6800 format) and for searching for data pattern as well as trigging sampling at predefined data pattern were implemented. Technology: MS-DOS, Borland Pascal.